System-on-Chip (SoC) integrates integrated circuits with different functions (such as central processing unit (CPU), graphics processing unit (GPU), memory, etc.) into a single chip for use in systems or subsystems by reducing feature size. However, reducing feature size to manufacture SoCs is becoming increasingly difficult and expensive. Chip design and heterogeneous integration packaging offer an alternative to SoCs.
There are at least five different chip design and heterogeneous integration packaging approaches:
(1) Chip partitioning heterogeneous integration (driven by cost and technology optimization);
(2) Chip disaggregation heterogeneous integration (driven by cost and semiconductor manufacturing yield);
(3) Heterogeneous integration of multi-systems with thin-film layers directly on laminated packaging substrates;
(4) Heterogeneous integration of multi-systems with intermediary layers without TSVs (2.3D IC integration);
(5) Heterogeneous integration of multi-systems with TSV intermediary layers (2.5D and 3D IC integration).
In chip partitioning heterogeneous integration, the logic and input/output functions of the SoC are partitioned into logic and I/O chip modules. These chip modules can be stacked (integrated) using front-end CoW (chip-on-wafer) or WoW (wafer-on-wafer) methods, and then assembled (integrated) onto a single packaging substrate using heterogeneous integration technologies. It should be emphasized that the front-end integration of chip modules can result in smaller packaging area and better electrical performance, though it is optional. For example, AMD’s EPYC shipped in 2019, and Intel’s Lakefield shipped in 2020.
In chip disaggregation heterogeneous integration, the SoC (such as the logic part) is divided into smaller chip modules (e.g., Logic 1, Logic 2, and Logic 3). These chip modules can be stacked (integrated) using front-end CoW or WoW methods, and then assembled onto a single packaging substrate using heterogeneous integration technologies. Again, front-end integration of the chip modules is optional. For instance, Xilinx’s FPGA shipped in 2013, AMD’s EPYC in 2019, and Intel’s Lakefield in 2020.
In heterogeneous integration of multi-systems with thin-film layers directly on laminated packaging substrates (2.1D IC integration), the SoC (e.g., CPU, logic, and high-bandwidth memory) is supported by a laminated packaging substrate with thin-film layers. This is driven by performance and form factor, used for high-density and high-performance applications. However, due to the flatness of the laminated substrate, the yield loss of thin-film layers is very high, and the technology is not yet in mass production.
In heterogeneous integration of multi-systems with intermediary layers without TSVs, the SoC (e.g., CPU, logic, and high-bandwidth memory) is supported by fine line/pitch RDL substrates (organic interposers), which are then placed on laminated packaging substrates (2.3D IC integration). This is also driven by performance and form factor and is used for high-density and high-performance applications. This technology is currently in small-scale production and is expected to capture part of the market share from 2.5D IC integration.
In heterogeneous integration of multi-systems with TSV intermediary layers (2.5D/3D IC integration), the SoC (e.g., CPU, logic, and high-bandwidth memory) is supported by passive (2.5D) or active (3D) TSV interposers, and then placed on laminated packaging substrates. This is driven by performance and form factor, used for ultra-high-density and high-performance applications. Since 2013, companies such as Xilinx, AMD, Intel, NVidia, Fujitsu, and Graphcore have shipped products using this technology. In the future, it will be used more in ultra-high-performance, high-density, and high-bandwidth products.
Chip scaling for SoCs will continue. Chip design and heterogeneous integration packaging offer an alternative for SoCs, especially at advanced nodes (smaller feature sizes) that most companies cannot afford. Moreover, chip design and heterogeneous integration packaging may reduce semiconductor manufacturing costs for products.
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