Most people haven’t even fully adopted PCIe 4.0, and even products with PCIe 5.0 are only available in limited quantities. However, manufacturers are unconcerned about this and have even begun launching products with PCIe 6.0. For example, the renowned controller manufacturer, Phison, has already started developing new controller chips for PCIe 6.0, which could potentially exceed speeds of 30GB/s. The PCIe 6.0 standard has been out for three years, and the dawn of its commercialization is now upon us.
01
Origins and Development of PCIe
In the ongoing evolution of computer technology, the efficiency of data transmission has always been a key factor limiting system performance. In the early days, traditional bus technologies like PCI (Peripheral Component Interconnect) dominated the connection of computer hardware. However, with the rapid advancement of computer hardware, especially the significant improvement in CPU performance and the emergence of various high-speed external devices, traditional bus technologies gradually began to show their limitations. For example, the bandwidth of the PCI bus was limited and could not meet the needs of high-speed graphics cards and large-capacity storage devices, becoming an obstacle to further improving system performance.
To address these issues, PCI Express (PCIe) was introduced. PCIe adopted a new serial connection method, replacing the parallel connection used by traditional PCI, significantly improving data transmission efficiency and stability.
PCIe 1.0 was officially released in 2003, marking a major breakthrough in computer bus technology. The unidirectional transmission speed of each lane in PCIe 1.0 reached 2.5Gbps, or 5Gbps for bidirectional, with a maximum transfer rate of 250MB/s per lane. Compared to the traditional PCI bus, PCIe 1.0 made a qualitative leap in transmission speed, better supporting the emerging high-speed devices like graphics cards, greatly enhancing computer graphics processing capabilities. In practice, PCIe 1.0-based graphics cards could run large 3D games more smoothly, providing players with an improved visual experience.
Subsequently, PCIe 2.0 was released in 2007. This version doubled the transmission speed per lane to 5Gbps (10Gbps bidirectional), increasing the bandwidth compared to PCIe 1.0, with a maximum transfer rate of 500MB/s per lane. This improvement allowed PCIe 2.0 to better support data-hungry storage and network devices. For instance, enterprise-level disk array systems using PCIe 2.0 saw a significant boost in data read/write speeds, enhancing the efficiency of enterprise data storage and processing.
The PCIe 3.0 version, released in 2010, further increased the transmission speed per lane to 8Gbps (16Gbps bidirectional), while maintaining compatibility with previous versions. It optimized the protocol, reduced latency, and improved data transmission efficiency, with a maximum transfer rate of 1GB/s per lane. PCIe 3.0 became widely used in high-end servers, workstations, and other devices, providing an efficient channel for data exchange between multi-core CPUs and high-speed storage and network devices, thereby driving the improvement of enterprise-level data processing capabilities.
PCIe 4.0, released in 2017, represented another significant milestone in the evolution of PCIe technology. It increased the transmission speed per lane to 16Gbps (32Gbps bidirectional), doubling the bandwidth compared to PCIe 3.0, with a maximum transfer rate of 2GB/s per lane. This substantial increase in bandwidth brought revolutionary changes to fields like data centers and high-end graphics cards.
In the data center sector, the rapid development of cloud computing and big data analytics has raised demands for faster data transmission and storage performance. PCIe 4.0 enabled servers to read and store vast amounts of data more quickly, greatly improving data processing efficiency. For example, solid-state drives (SSDs) using PCIe 4.0 can achieve sequential read speeds exceeding 7000MB/s and write speeds over 5000MB/s, a significant improvement over PCIe 3.0 SSDs, making them suitable for the high-speed storage demands of data centers.
In the high-end graphics card sector, PCIe 4.0 also played an important role. With the increasing demand for more detailed game graphics, PCIe 4.0 provided faster data transfer channels for graphics cards, enabling them to retrieve data from memory more quickly and improving frame rates and image quality. For example, in running large 3D games at 4K resolution, PCIe 4.0-based graphics cards were able to render frames more smoothly, reducing stuttering and providing players with a more immersive gaming experience.
PCIe 5.0, released in 2019, continued the trend of rapid development in PCIe technology. It increased the transmission speed per lane to 32Gbps (64Gbps bidirectional), doubling the bandwidth compared to PCIe 4.0, with a maximum transfer rate of 4GB/s per lane. PCIe 5.0 not only greatly enhanced bandwidth but also optimized signal integrity, power management, and other aspects, further improving system performance and stability.
In data centers, PCIe 5.0 enabled servers to better support large-scale virtualization and cloud computing applications. Through PCIe 5.0, servers could connect more high-speed devices, such as high-speed network cards and high-performance GPUs, for more efficient data processing and transmission. In artificial intelligence (AI), PCIe 5.0 supported high-speed communication between GPUs, accelerating the training and inference of AI models. For instance, in large AI training projects, multiple GPUs connected via PCIe 5.0 could exchange data faster, improving training efficiency and shortening the training time.
02
PCIe 6.0 Begins Commercialization, Domestic Manufacturers Begin to Layout
In January 2022, PCI-SIG officially released the PCIe 6.0 standard, marking the largest change in the technology’s history. Not only did the bandwidth continue to increase, but the underlying architecture and functional features also underwent dramatic changes. On January 27, 2022, Rambus became the first to release a controller fully compliant with PCIe 6.0, supporting all new features. This controller is mainly aimed at high-performance computing, data centers, AI and machine learning, automotive, IoT, defense, aerospace, and other cutting-edge fields. It supports a PCIe 6.0 data transfer rate of 64GT/s, with a single x1 lane providing 8GB/s of unidirectional physical bandwidth (equivalent to PCIe 4.0 x4), and up to 128GB/s for x16, or 256GB/s bidirectional. PCIe 6.0 has now begun to be commercialized globally, and many companies are launching products based on PCIe 6.0 technology.
In August of the previous year, Micron released the industry’s first PCIe 6.0 SSD. These SSDs leverage PCIe 6.0’s high bandwidth to achieve higher read and write speeds. Micron indicated that these high-performance SSDs belong to its Micron 9550 NVMe SSD series, though official details regarding the memory chips and controllers used have not been disclosed. It was only mentioned that PCIe 6.0 will be used for data transmission, and the SSD is primarily designed for data centers, not consumer use. Micron also revealed that the sequential read speed of these SSDs can reach up to 26GB/s, more than 85.7% faster than current consumer-grade PCIe 5.0 SSDs, though this speed is still short of the maximum potential of PCIe 6.0, which is expected to reach around 32GB/s. Clearly, this SSD is still an early-stage product.
In November 2024, Intel will release its Xeon Diamond Rapids processors, which will support PCIe 6.0. In the same month, AMD announced its second-generation Versal Premium series adaptive SoC chips, the first FPGA industry device to support CXL 3.1, PCIe 6.0, and LPDDR5 memory in its hard IP.
With the commercialization of PCIe 6.0 beginning, domestic manufacturers are also actively entering this field.
Storage solution provider Phison announced that it is actively developing a PCIe 6.0 SSD controller chip using advanced 4nm process technology, model SM8466. This controller chip is targeted at the enterprise market, aiming to meet the growing demand for high-performance storage. The SM8466 controller will fully support PCIe 6.0 x4 lanes, with a theoretical bandwidth of up to 30.25 GB/s, representing a significant bandwidth increase over the PCIe 5.0 standard.
However, domestic manufacturers face some challenges in the development of PCIe 6.0. On one hand, compared to internationally renowned companies, domestic manufacturers still have a gap in terms of technical accumulation and R&D investment, requiring further efforts to improve their technology. On the other hand, the PCIe 6.0 technology ecosystem is still being refined, and domestic manufacturers need to actively participate in the ecosystem’s development and strengthen cooperation with upstream and downstream companies to jointly promote the development and application of PCIe 6.0.
03
PCIe 7.0 Arrives Before PCIe 6.0 Even Takes Off
It is worth noting that the next generation, PCIe 7.0, is already on the horizon, and it introduces optical communication connections for the first time.
PCIe 6.0 is considered the biggest change to PCIe in nearly 20 years, but at this point, traditional approaches have largely reached their limits, and further improvements are extremely difficult. At the PCIG-SIG DevCon 2024 developer conference, Cadence demonstrated a new direction for PCIe 7.0, incorporating its own unique optical connection solution, achieving a send/receive rate of 128GT/s in a real, low-latency, untimed, linear optical connection system. This means that its x16 bidirectional bandwidth could reach 512GB/s, doubling once again.
The traditional electrical layer has reached its limits. As data transmission speeds continue to rise, traditional electrical signal transmission faces issues like signal attenuation and interference, making it hard to meet the needs of high-speed data transmission. Optical signals, with their fast transmission speeds, low loss, and strong resistance to interference, have become the key to solving the problem of high-speed data transmission in PCIe 7.0.
The PCIe 7.0 specifications include the following features:
- A raw bit rate of up to 128GT/s, with a maximum bidirectional data transfer rate of 512GB/s via x16 configuration.
- The use of PAM4 (four-level pulse amplitude modulation) signals, which encode four different amplitude levels on signals to increase the information density transmitted per unit time.
- Optimized channel parameters and transmission distances to ensure high data transfer rates and stability over longer physical distances.
- Continued improvements in low-latency performance, enhanced system robustness, and data transfer accuracy to meet the real-time and data integrity demands of critical applications.
- Emphasis on energy efficiency, reducing the energy consumption per bit of data transmitted.
- Good compatibility, maintaining backward compatibility with all previous PCIe generations, ensuring seamless integration with hardware devices from earlier PCIe versions.
- The addition of optical interconnects, offering a new option in addition to traditional copper interconnects, capable of transmitting signals over longer distances with lower latency.
PCIe 7.0 technology will not initially be applied to consumer products. It will primarily be used in commercial and enterprise-level applications such as data centers, AI machine learning, high-performance computing, and network communications. Specifically, PCIe 7.0 will meet the high-bandwidth needs of future 800G Ethernet, AI/ML, large-scale data centers, HPC, quantum computing, and public cloud applications. The full PCIe 7.0 specification is expected to be released in 2025, which means supported devices may not arrive until 2026, and widespread enterprise-level products may not be available until 2028-2029.
04
PCIe Will Become a Key Component in AI Infrastructure Market
It is clear that from PCIe 6.0 onwards, manufacturers will no longer focus on the consumer market but will instead concentrate on commercial and enterprise-level product fields such as data centers and AI infrastructure.
As AI technology rapidly evolves, AI applications require ever-increasing data transmission speeds and bandwidth. During AI model training, massive amounts of data must be transmitted at high speed between CPUs, GPUs, and storage devices. For example, when training a large language model, vast amounts of text data need to be read from storage and processed by GPUs, and the computation results must then be transferred back to storage. Slow data transmission speeds would significantly prolong training times and reduce AI application efficiency.
Traditional data transmission technologies are gradually showing limitations when faced with the high demands of AI applications. For instance, while traditional Ethernet technology is widely used for network connections, its bandwidth is limited, making it difficult to meet AI’s high-speed data transfer requirements. In AI training scenarios, large amounts of data need to be transmitted in a short period, and Ethernet’s bandwidth bottleneck can lead to data transfer delays, affecting AI model training outcomes.
NVIDIA’s NVLink technology is designed specifically for high-speed communication between GPUs. It offers extremely high bandwidth and low latency, enabling fast data transfer between multiple GPUs. For example, NVIDIA’s DGX series supercomputers use NVLink to connect multiple GPUs, significantly improving AI model training efficiency.
While major chip companies are developing their own interconnect technologies, such as NVIDIA’s NVLink, AMD’s Infinity Fabric, and Ethernet interconnects, PCIe remains the preferred interface for server racks. As PCIe 6.0 and above are deployed and PCIe 7.0 specifications are nearing approval, PCIe will continue to be a critical player in high-speed interconnection.
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