Common Structures in Advanced Packaging
| Structure Name | English Abbreviation | Description | Application Scenarios |
|---|---|---|---|
| Through-Silicon Via | TSV | Holes are made in silicon and filled with copper to vertically connect chips | 3D stacking, HBM, high-performance computing |
| Through-Glass Via | TGV | Similar to TSV but with glass as the substrate | High-frequency RF, SiP, substrate replacement |
| Cu Pillar | Cu Pillar | Fine-pitch interconnect between chip and substrate; electroplated copper with Sn cap | Flip Chip, FCBGA |
| Redistribution Layer | RDL | Redistributes chip I/O; usually multiple metal layers | Fan-Out, InFO, 2.5D packaging |
| Gold Bump | Au Bump | For gold wire bonding or TCB bonding | High-reliability packaging, optoelectronic chips |
| Micro Bump | µBump | Fine-pitch bumps (<30μm) for die-to-die interconnection | 2.5D, 3D-IC, HBM, Chiplet |
| Solder Ball | Solder Ball | For soldering to substrates | Used in almost all chip packaging |
The structures listed above are essentially the “core” of advanced packaging processes. Why electroplating is used instead of other metallization methods:
Take the cover image as an example: in advanced packaging, the structure height needs to reach at least several microns to several hundred microns. Only electroplating has a plating speed that can meet this requirement. At a current density of 1 ASD, the copper plating rate is 0.2 µm/min. Generally, the current density can be adjusted within a range of 1–15 ASD, so the plating rate can reach an impressive 3 µm/min. This is unattainable by typical PVD or CVD methods.
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