Here is a detailed analysis of the principles behind DRAM (Dynamic Random Access Memory) technology, covering manufacturing processes, internal structure of Ranks and Banks, the role of ODT, read/write operations, as well as LPDRAM and DDR product iterations.
| Memory | Data Rate (Gbps) | Bandwidth (GB/s) | Relative Shore Density | Relative Areal Density | Process Technology | Product (Die) |
|---|---|---|---|---|---|---|
| DDR5 | 4.8 | 307.2 | 1.00 | 1.00 | Intel 7 | Sapphire Rapids (XCC) |
| DDR5 | 4.8 | 460.8 | 1.37 | 0.65 | TSMC N6 | Genoa (IOD) |
| LPDDR5 | 6.4 | 51.20 | 0.63 | 1.28 | TSMC N4 | Apple A16 |
| GDDR6 | 18.0 | 576.0 | 1.41 | 2.15 | TSMC N7 | RDNA 2 (Navi 22) |
| GDDR6X | 21.0 | 1008 | 1.76 | 1.90 | SS 8LPP | Ampere (GA102) |
| GDDR6X | 21.0 | 1008 | 1.8 | 2.47 | TSMC 4N | Ada Lovelace (AD102) |
| HBM3 | 5.2 | 3994 | 8.60 | 9.48 | TSMC 4N | Hopper (GH100) |
I. Manufacturing Technology
1. Process Technology and Core Innovations
DRAM is manufactured using Complementary Metal-Oxide-Semiconductor (CMOS) processes. The main objective is to integrate more memory cells per unit area while improving performance. Key technologies include:
- High Aspect Ratio Capacitor: Each memory cell consists of one transistor (T) and one capacitor (C) in a 1T1C configuration. The capacitor stores charge (representing 0/1). As process nodes shrink (e.g., sub-10nm FinFET), capacitors maintain storage capacity through 3D stacking (e.g., vertical pillar capacitors) to avoid data loss due to leakage.
- HKMG (High-k Metal Gate): Reduces transistor leakage and improves cell stability, which is critical for deep sub-micron processes.
- 3D Stacking and Multi-Chip Packaging: Multiple DRAM dies are vertically or inter-layer stacked using TSV (Through-Silicon Via) or wafer bonding techniques to form high-capacity chips (e.g., 16GB per die), typically packaged in BGA (Ball Grid Array) form.
2. Key Manufacturing Processes
- Wafer Fabrication:
- Oxidation & Lithography: Silicon dioxide is grown on the wafer surface; lithography defines the transistor and capacitor structures.
- Ion Implantation: Doping creates the source, drain, and gate of the transistor.
- Capacitor Formation: Capacitors are built above the transistor, using dielectric materials like silicon nitride to enhance density.
- Packaging & Testing:
- Dicing & Bonding: Wafers are diced into dies and connected to substrates via wire bonding or flip-chip techniques.
- Module Assembly: Multiple dies are assembled into a Rank on a DIMM (Dual In-line Memory Module), with PCB traces handling interconnects, followed by testing for speed, power, and reliability.
II. Internal Structure of DRAM
1. Rank Definition and Architecture
A Rank is a group of DRAM chips sharing data, address, and control buses, functioning as the basic addressing unit in memory systems. For example, a DDR4 DIMM often contains 1 or 2 Ranks, each comprising 8 dies (64-bit data width, or 72-bit with ECC).
- Data Width: A single Rank has a fixed width (e.g., 64 bits); multiple Ranks can work in parallel (e.g., in dual-channel mode) to increase bandwidth.
2. Bank Hierarchical Structure
Each DRAM die has a multi-level hierarchy to improve access efficiency:
- Bank Group (BG): Dies are divided into several Bank Groups (e.g., DDR4 typically has 4 BGs), each operating independently for parallel activation and reduced latency.
- Bank: Each BG has multiple Banks (e.g., 8 Banks per BG, 32 Banks total per die). A Bank is a standalone memory array that can be activated or precharged individually.
- Memory Array: Banks consist of Rows and Columns. Row addresses are selected using RAS (Row Address Strobe), and column addresses via CAS (Column Address Strobe).
3. Prefetch Technology
DRAM uses 8n prefetch architecture (e.g., DDR4’s 8n prefetch), meaning 8× the data bus width is read per clock cycle from the memory array (e.g., 512 bits per access for a 64-bit bus). This data is transferred in two chunks via the internal Data Buffer on each clock edge, achieving effective data rates (e.g., 2400MT/s = 300MHz × 2 × 8n).
| DRAM historical names | Year of Release | BUS Frequency (MHz) | Data Transfer Rate (MT/s) | Operating Voltage (V) | Topology | Prefetch | Memory connection form |
|---|---|---|---|---|---|---|---|
| SDRAM | 1993 | 100~166 | 100~166 | 3.3V | T-Branch | 1n | Multiple branches |
| DDR | 2000 | 133~200 | 266~400 | 2.5V | T-Branch | 2n | Multiple branches |
| DDR2 | 2003 | 266~400 | 533~800 | 1.8V | T-Branch | 4n | Multiple branches |
| DDR3 | 2007 | 533~800 | 1066~1600 | 1.5V | Fly-by | 8n | Multiple branches |
| DDR4 | 2014 | 1066~1600 | 2133~3200 | 1.2V | Fly-by | 8n | Point to point |
| DDR5 | 2019 | 1600~3200 | 3200~6400 | 1.1V | Fly-by | 16n | Point to point |
III. Role of ODT (On-Die Termination)
1. Signal Integrity Optimization
ODT is a programmable resistor network integrated into DRAM dies, mainly to address impedance matching issues in high-speed signal transmission:
- In DDR systems, address/control signals follow a fly-by topology (daisy-chained), and impedance mismatch between transmission lines (e.g., 50Ω PCB traces) and chip inputs causes signal reflection and ringing, impacting timing accuracy.
- ODT dynamically matches transmission line impedance using internal resistors (e.g., 34Ω, 50Ω, 68Ω), absorbing reflections and improving signal quality—especially critical at high frequencies (e.g., DDR5 above 6400MT/s).
2. Reduced Design Complexity and Power Consumption
ODT replaces external termination resistors, reducing PCB layer count and component cost.
- It activates only during data transmission (e.g., during reads), and powers down during idle, reducing power consumption by ~20–30% compared to fixed external resistors.
IV. Read/Write Operations and Command Mechanism
1. Basic Command Set
DRAM operations are driven by control signals (CS#, RAS#, CAS#, WE#) and address buses. Core commands include:
- ACTIVATE: Opens a row in a specific Bank, loading data into the Sense Amplifier.
- READ/WRITE: Selects a column within the activated row to read data into the Data Buffer or write new data.
- PRECHARGE: Closes the active Bank and prepares it for the next operation.
- REFRESH: Recharges cell capacitors to prevent data loss due to leakage. Includes Auto-Refresh and Self-Refresh (low-power mode).
2. Read Operation Flow
- Activation: The ACTIVATE command specifies the Rank, Bank Group, Bank, and Row. The Sense Amplifier reads the data into a buffer.
- Reading: A READ command selects the column address. The 8n prefetch mechanism fetches data from the Sense Amplifier into the Data Buffer and outputs via the DQ bus.
- Data Transfer: Data is output on both rising and falling clock edges (DDR), synchronized with the DQS (Data Strobe), which ensures accurate timing and counters clock skew.
3. Write Operation Flow
- Activation: Same as read; the target row is opened.
- Writing: The WRITE command sends data from the external controller via the DQ bus. Synchronized by DQS, data is stored in the Data Buffer and then written into the memory array.
- Precharge: After writing, the Bank is closed and data is held in the capacitor for retention until the next access.
Clock and Signal Synchronization
- System Clock (CK): Global clock used for synchronizing commands and addresses; DDR4 typical frequency is 1600MHz (equivalent to 3200MT/s).
- Source-Synchronous Clock (DQS): Each Rank has its own DQS signal strictly aligned with data for precise high-speed sampling, especially important with multiple parallel Ranks.
- Differential Signaling: Key signals (e.g., CK/CK#, DQS/DQS#) use differential transmission to suppress common-mode noise and improve immunity to interference.
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