In the semiconductor industry, it’s common to hear manufacturers say, “We have a monthly capacity of 50,000 wafers.” It sounds impressive, but if you try to convert that number into actual chip quantities, you’ll find there’s a lot more to it.
First, let’s clarify three terms: a wafer is a round disc made of silicon, the raw material for chips; a die is one of the many small rectangles on a wafer — an unpackaged “bare chip”; and a chip is a finished product, cut from the wafer and packaged — like a pizza (wafer) cut into slices (die) and packed into a box (chip).
Common wafer sizes today are:
- 6-inch (150mm diameter): older processes, special applications.
- 8-inch (200mm diameter): mature processes, mainly used for analog chips, power devices, MEMS, etc.
- 12-inch (300mm diameter): currently mainstream, used for advanced logic chips and memory chips.
The larger the diameter, the greater the usable area and the more chips that can be produced.
Take a 300mm wafer as an example. Its theoretical area is π × radius² ≈ 70,685 mm². But not all of that is usable, due to three main factors:
- Edge Exclusion: The outer 5–10mm of the wafer is not usable due to processing precision and fixture contact issues, which result in poor yield. For a 300mm wafer, excluding a 5mm edge gives an effective radius of 145mm → usable area ≈ 66,000 mm².
- Scribe Lanes: There must be gaps of 50–150 microns between dies to allow cutting with lasers or saw blades. These gaps consume space.
- Non-product Structures: Process control structures (PCM) and test circuits are also placed on the wafer to monitor production quality, which takes up additional space.
In practice, only about 90% of the theoretical area can be used.
How many dies can be produced from one wafer depends on the area of a single die, which is determined by chip design:
- Smartphone SoCs: 100–150 mm²
- Large GPUs: 400–800 mm² (massive)
- DRAM dies: 20–30 mm²
- Microcontrollers (MCUs): 2–10 mm²
Once you know the usable area and die size, you also have to consider yield — the proportion of dies that pass testing. Yield typically ranges from 60% to 95%, but it’s much lower for new processes. Large chips also have lower yields due to a higher probability of defects. So the estimation formula is:
Usable die count ≈ (Wafer usable area ÷ die area) × yield
Wafer usable area = π × (effective radius)² × area utilization rate (after deducting scribe lanes, etc.)
For example, a 300mm wafer with a 5mm edge exclusion has an effective radius of 145mm, and a usable area of ≈ 66,052 mm². After deducting losses (90% area utilization), you get 59,447 mm².
If each die is 5×5mm (25 mm²), you can fit around 2,378 dies theoretically.
At an 80% yield, you get about 1,902 good chips.
Different chip types produce vastly different yields. On a 300mm wafer with 80% yield and 90% area utilization:
- DRAM dies (25 mm²): ~1,900 units
- Smartphone SoCs (120 mm²): ~400 units
- Large GPUs (600 mm²): ~80 units
- Small MCUs (4 mm²): over 12,000 units
This explains why, with the same wafer capacity, memory manufacturers often ship many times more units than GPU makers.
Yield has a huge impact on output. In the early stages of a new process, yield might be just 30–50%. Mature processes can exceed 90%. To reduce losses, some manufacturers “downgrade” chips — for instance, if part of a GPU is defective, they may disable those features and sell it as a lower-end model, increasing usable output.
Back to the original question: if a DRAM manufacturer has a monthly capacity of 50,000 300mm wafers, and each wafer yields 1,900 good dies, that’s 95 million DRAM dies per month.
If one memory stick uses 8 dies, the monthly production would be about 11.875 million memory sticks. Of course, this is a rough estimate — actual production varies with design, packaging, order specs, and other factors.
So next time someone says, “We produce XX thousand wafers per month,” you can tell them: it depends on the die size and yield — otherwise it’s like asking how many slices you can get from a pizza. It all depends on how you cut it, and the difference can be huge.
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