Today, let’s talk about chip packaging and testing (commonly referred to as “packaging and testing”).
This part is also known in the industry as the back-end process, typically handled by OSAT (Outsourced Semiconductor Assembly and Test) factories.
01
The purpose of chip packaging
First, let’s talk about packaging.
The term “packaging” is something we hear quite often. It mainly refers to the process of transforming the bare chip (die) on the wafer into the final product chip.
There are two main reasons for packaging.
One is to protect the fragile die, preventing physical damage from bumps and also preventing the circuits on the die from being corroded by impurities in the air.
The second is to make the chip better suited to the requirements of the usage scenario.
Chips have many application scenarios, and each scenario has different requirements for the chip’s appearance. Proper packaging allows the chip to function better.
We often see many different shapes of chips, which are actually just different types of packaging.
02
The development stages of chip packaging
The packaging process emerged with the advent of chips and has a history of over 70 years.
Overall, the packaging process has gone through five development stages:
| Stage | Start Time | Packaging Form | Specific Typical Packaging Forms |
|---|---|---|---|
| First | ~1970s | Through-Hole Packaging | TO, CDIP, PDIP, SIP |
| Second | 1980s~1990s | Surface-Mount Packaging | PLCC, PQFP, SOP, PQFN, SOT, DFN |
| Third | 1990s~2000s | BGA & WLP & CSP | PBGA, CBGA, EBGA, FC-BGA, CSP |
| Forth | 2000s~2010s | MCM, 2.5D/3D, Bumping | MCM-C/D/L, 2.5D/3D, Bumping |
| Fifth | 2010s~ | SiP, TSV, RDL, Fan-Out, Fan-In | SiP, TSV, RDL, Fan-Out, Fan-In |
Next, let’s go through them one by one.
✅ Traditional Chip Packaging
The earliest transistors used TO (Transistor Package). Later, DIP (Dual In-line Package) was developed.
The familiar shape of a transistor is the TO package.
Later on, PHILIP developed the SOP (Small Outline Package), which gradually led to the creation of SOJ (J-lead Small Outline Package), TSOP (Thin Small Outline Package), VSOP (Very Small Outline Package), SSOP (Shrink Small Outline Package), TSSOP (Thin Shrink Small Outline Package), SOT (Small Outline Transistor), and SOIC (Small Outline Integrated Circuit), among others.
The packaging during the first and second stages (1960-1990) primarily consisted of through-hole package (THP) and surface-mount package (SMP), both of which are considered traditional packaging.
Traditional packaging mainly relies on leads to establish an electrical connection between the die and the outside world.
These traditional packages are still quite common today. Especially for older classic chip models, which do not have high performance or volume requirements, this low-cost packaging method is still used.
In the third stage (1990-2000), the IT technological revolution accelerated, making chips more complex and requiring more pins. At the same time, the miniaturization of electronic products demanded that chip sizes continue to shrink.
At this point, BGA (Ball Grid Array) packaging began to appear and became mainstream.
BGA is still considered a traditional package. Its pins are located at the bottom of the chip in large numbers, making it ideal for chips that require many connections. Additionally, compared to DIP, BGA has a more compact size, making it suitable for miniaturized devices.
Similar to BGA, there are also LGA (Land Grid Array) and PGA (Pin Grid Array) packages. You may have noticed that the most familiar CPUs use these three types of packaging.
| Name | BGA | LGA | PGA |
|---|---|---|---|
| Full Name | Ball Grid Array | Land Grid Array | Pin Grid Array |
| Applicable Scenarios | Applicable to low-power devices and laptops | Applicable to most Intel processors | Applicable to AMD processors |
| Advantages | Small size, occupies less space | Good contact, good heat dissipation performance | Easy to replace, higher pin strength |
| Disadvantages | The maintenance cost is high | The pins are prone to damage | The pins are prone to damage, and the maintenance is complex |
✅ Advanced Chip Packaging
At the end of the 20th century, chip-level packaging (CSP), wafer-level packaging (WLP), and flip-chip packaging began to rise. Traditional packaging started evolving into advanced packaging.
Compared to packaging like BGA, chip-level packaging (CSP) emphasizes even smaller size (the packaging area is no more than 1.2 times the chip area).
Wafer-level packaging is a type of chip-level packaging, where the package size is close to that of the bare chip.
When we discuss specific processes next time, we will mention that packaging includes a cutting process. In traditional packaging, the wafer is first cut and then packaged. In wafer-level packaging, the wafer is first packaged, then cut, with a different process flow.
The invention of flip-chip packaging dates back to the 1960s when IBM first developed the technology. However, it wasn’t until the 1990s that this technology began to gain widespread use.
With flip-chip packaging, metal wires are no longer used for connections. Instead, the wafer is flipped over and connected electrically to the substrate through bumps on the wafer.
Compared to the traditional metal wire method, flip-chip packaging has more I/O (input/output) channels, shorter interconnect lengths, and better electrical performance. Additionally, it has advantages in terms of heat dissipation and package size.
The emergence of advanced packaging catered to the demands of the time.
It uses advanced design and processes to reconfigure the packaging at the chip level, bringing more pins, smaller sizes, and higher system integration, greatly enhancing system performance.
After entering the 21st century, with the further explosion of mobile communication and the internet revolution, chip packaging has advanced further in the direction of higher performance, miniaturization, lower cost, and higher reliability. Advanced packaging technology has entered a period of rapid development.
During this period, the internal layout of chips began to evolve from two-dimensional to three-dimensional space (by stacking multiple dies together), leading to the emergence of 2.5D/3D packaging, through-silicon vias (TSV), re-distribution layers (RDL), fan-in/fan-out wafer-level packaging, system-in-package (SiP), and other advanced technologies.
As chip manufacturing processes began to reach the limits of Moore’s Law, these advanced packaging technologies became the “lifeline” to continue Moore’s Law.
03
Key technologies for advanced Chip packaging
✅ 2.5D/3D Packaging
2.5D and 3D packaging are both methods of chip stacking.
2.5D packaging technology allows two or more types of chips to be placed in a single package, enabling lateral signal transmission, which enhances package size and performance.
The most widely used 2.5D packaging method involves placing memory and logic chips (such as GPUs or CPUs) into a single package via a silicon interposer.
2.5D packaging requires core technologies such as Through-Silicon Vias (TSV), Re-Distribution Layers (RDL), and micro bumps.
3D packaging is a technique where two or more chips are stacked vertically within the same package.
The main difference between 2.5D and 3D packaging is that in 2.5D packaging, wiring and drilling are done on the interposer, while in 3D packaging, drilling and wiring are done directly on the chips, connecting the stacked layers. 3D packaging generally has higher requirements and is more complex.
Both 2.5D and 3D packaging originated from the needs of FLASH memory (NOR/NAND) and SDRAM. The famous HBM (High Bandwidth Memory) is a typical application of 2.5D and 3D packaging. By integrating HBM with a GPU, the GPU’s performance can be further enhanced.
HBM stacks multiple DRAM chips vertically using TSV and other advanced packaging techniques, and is packaged together with the GPU on an interposer. The DRAM stacking within HBM is considered 3D packaging, while the integration of HBM and GPU on the interposer is 2.5D packaging.
Many of the industry’s new technologies, such as CoWoS, HBM, Co-EMIB, HMC, Wide-IO, Foveros, SoIC, X-Cube, etc., have evolved from 2.5D and 3D packaging.
✅ System-in-Package (SiP)
You may have heard of SoC (System on Chip). The main chip in our phones is an SoC chip.
Simply put, SoC integrates multiple chips with different functions into a single chip, maximizing size reduction and achieving high integration.
However, designing an SoC is quite complex, and it often requires obtaining IP (intellectual property) licenses from other companies, which increases costs.
SiP (System in Package) is different from SoC.
SiP directly takes multiple chips and packages them in a single package, either side by side or stacked (2.5D/3D packaging).
Although SiP does not have the same level of integration as SoC, it is sufficient, reduces size, and, most importantly, is more flexible and lower in cost (since it avoids the complicated IP licensing process).
The industry term “Chiplet” refers to SiP’s concept—combining multiple dies (chips) that serve specific functions and interconnecting them via die-to-die technology to form a larger chip.
✅ Through-Silicon Via (TSV)
We have frequently mentioned TSV (Through-Silicon Via).
The principle of TSV is quite simple: vertical vias are etched on a silicon substrate and filled with metal to establish vertical electrical connections between the top and bottom layers.
Because TSV allows for the shortest vertical interconnection distances and offers higher strength, it is easier to achieve miniaturization, high density, and high performance. This makes TSV particularly suitable for stacked packaging (3D packaging).
We will introduce the specific process of TSV in the next issue.
✅ Re-Distribution Layer (RDL)
RDL involves depositing metal layers and corresponding dielectric layers on the chip’s surface, forming metal wiring and redesigning the I/O ports into new, larger areas, creating a surface array layout to enable the connection between the chip and the substrate.
In essence, RDL rewires within the silicon substrate to ensure electrical connectivity between the upper and lower layers. In 3D packaging, if different types of chips are stacked with misaligned interfaces, RDL is used to align the I/Os of the chips.
If TSV extends the Z-plane, RDL extends the X-Y plane. Many industry technologies, such as WLCSP, FOWLP, INFO, FOPLP, EMIB, etc., are based on RDL technology.
✅ Fan-In/Fan-Out Wafer-Level Packaging
WLP (Wafer-Level Packaging) can be divided into Fan-In WLP and Fan-Out WLP.
Fan-In WLP directly performs packaging on the wafer, cuts it afterward, and completes the wiring within the chip’s size. The package size is the same as the chip size.
Fan-Out WLP uses wafer reconfiguration technology, where the cut chips are rearranged onto an artificial carrier board. Then, wafer-level packaging is done, and the chips are cut again. Wiring can be done both inside and outside the chip, resulting in a larger packaging area than the chip area, but providing more I/O connections.
Currently, the most widely mass-produced is Fan-Out WLP.
The above provides a simple introduction to some background knowledge of packaging.
Organized from the internet
Related:
- 2nm Process Nodes Reveal Critical Chip Yield Issues
- Discover SIP Technology and Its Role in 16GB DDR4 Chips
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