Chip Design Unveiled: Step-by-Step Process Overview

Introduction: The Significance of Chip Design

In an era where technology touches every aspect of our lives, chip design stands as the foundation of this digital revolution. It is the intricate process of creating semiconductor chips (Sand made into Chips, Why did Chips sell as Sand now?) that power everything from smartphones to medical devices, enabling seamless connectivity and unprecedented computing power.

Chip design is divided into front-end design and back-end design. There is no strict boundary between front-end design (also known as logic design) and back-end design (also known as physical design). Design related to processes is considered back-end design.

Front-End Chip Design Flow

1. Specification Development

Chip specifications, much like a list of functionalities, are the design requirements provided by customers to chip design companies (referred to as Fabless companies, those without their own fabrication facilities). These specifications encompass specific functionalities and performance requirements that the chip needs to meet.

2. Detailed Design

Based on the specifications provided by the customer, Fabless companies develop design solutions and detailed implementation architectures, dividing the module functionalities.

3. HDL Coding

Hardware Description Languages (HDL), such as VHDL or Verilog HDL (usually the latter is used by industry companies), are used to describe module functionalities through code. This involves representing the actual hardware circuit functionalities using HDL language to generate RTL (Register Transfer Level) code.

4. Simulation Verification

Simulation verification involves checking the correctness of the coded design against the standards set in the initial specifications. The ultimate benchmark is whether the design precisely fulfills all the requirements stated in the specifications. Specifications serve as the gold standard for design accuracy. Any deviations or failure to meet specifications necessitate the revision of the design and coding. The design and simulation verification process is iterative, continuing until verification results demonstrate full compliance with specification standards.

5. Logic Synthesis – Design Compiler

Upon successful simulation verification, logic synthesis is conducted. The outcome of logic synthesis is the translation of the design’s implemented HDL code into a gate-level netlist. Synthesis involves setting constraint conditions and aiming for target parameters in terms of area, timing, and other criteria. The logic synthesis relies on specific synthesis libraries, and different libraries have distinct characteristics in terms of standard cell size and timing parameters. Consequently, the choice of synthesis library affects the differences in timing and area of the resulting circuit. Typically, after synthesis is completed, another round of simulation verification is performed (referred to as post-simulation, with the earlier phase being pre-simulation).

One of the logic synthesis tools is Synopsys’ Design Compiler.

6. STA – Static Timing Analysis

Static Timing Analysis (STA) falls within the realm of verification. Its primary purpose is to validate the circuit’s timing by examining whether the circuit violates setup time and hold time requirements. This is fundamental knowledge in digital circuits. When a register experiences violations in these two timing parameters, correct data sampling, and output become impossible. Consequently, digital chip functionality built upon registers is bound to encounter issues.

One of the STA tools is Synopsys’ Prime Time.

7. Formal Verification

Also within the domain of verification, formal verification assesses the post-synthesis netlist from a functional perspective (as opposed to STA, which focuses on timing). A common approach is equivalence checking, where the functionality of the post-synthesis netlist is compared against the functionally validated HDL design. The aim is to determine whether they are functionally equivalent, ensuring that logic synthesis has not altered the original circuit functionality described in HDL.

A formal verification tool is Synopsys’ Formality.

In terms of design progression, the result of the front-end design yields the gate-level netlist of the chip’s circuitry.

Back-End Chip Design Flow

1. DFT – Design For Test

Design For Test (DFT) focuses on incorporating testability within chip designs. Chips often include built-in test circuits, and the purpose of DFT is to consider testing during the design phase. A common DFT method involves inserting scan chains into the design and converting non-scan elements (such as registers) into scan elements. DFT is detailed in some books, and referencing images can aid in understanding.

DFT tool: Synopsys’ DFT Compiler.

2. FloorPlan – Layout Planning

FloorPlan involves placing macroblocks within a chip and determining the overall placement of various functional circuits such as IP modules, RAM, I/O pins, and more. FloorPlan directly affects the chip’s final area.

Tool: Synopsys’ Astro.

3. CTS – Clock Tree Synthesis

Clock Tree Synthesis (CTS) is the process of routing the clock signals. Given the global role of clock signals in digital chips, their distribution should be symmetrical, connecting to various register units. This minimizes clock delay differences when the clock reaches different registers from the same source. This is why clock signals require separate routing.

CTS tool: Synopsys’ Physical Compiler.

4. Place & Route – Routing

In this context, Place and route refers to the general signal routing, including the interconnections between various standard cells (basic logic gate circuits). For instance, the commonly heard terms like “0.13um process” or “90nm process” indicate the minimum metal width achievable in routing, which corresponds to the microscopic channel length of MOS transistors.

Tool: Synopsys’ Astro.

5. Parasitic Parameter Extraction

Due to the inherent resistance of wires, mutual inductance between adjacent wires, and coupling capacitance, signal noise, crosstalk, and reflections can occur within the chip. These effects can lead to signal integrity issues, resulting in voltage fluctuations and variations. Severe cases can cause signal distortion errors. Extracting parasitic parameters for further analysis and validation is crucial for analyzing signal integrity problems.

Tool: Synopsys’ Star-RCXT.

6. Physical Layout Verification

Functional and timing validation of the completed routed physical layout is essential. Numerous verification aspects include LVS (Layout vs. schematic) Verification: Comparing the physical layout against the gate-level circuit schematic generated from logic synthesis. DRC (Design Rule Checking): Verifying compliance with design rules, such as wire spacing and width, to meet fabrication requirements. ERC (Electrical Rule Checking): Detect violations of electrical rules, such as shorts and open circuits. And more.

Tool: Synopsys’ Hercules.

Words in the end

The actual backend process also includes circuit power analysis and Design for Manufacturing (DFM) issues that arise as manufacturing processes continue to advance. These aspects are not elaborated upon here.

Upon completion of physical layout verification, the entire chip design phase is finalized. The next step involves chip fabrication. The physical layout, in GDS II file format, is handed over to the chip manufacturing foundry. The foundry fabricates the actual circuit on a silicon wafer, followed by packaging and testing, resulting in the physical chip that we see.

In this stage, the manufactured chip undergoes various manufacturing steps, including photolithography, etching, doping, and metallization, to create intricate circuitry based on the designed layout. The final product is then ready for integration into electronic devices and systems.

FAQs

1. What is chip design? Chip design is the process of creating semiconductor chips that power electronic devices by integrating transistors and circuits.
2. Why is chip design important? Chip design is crucial as it underpins technological advancements, enabling devices to be smaller, faster, and more capable.
3. How long does the chip design take? The timeline varies, but it can take several months to years, depending on complexity and technological advancements.
4. What challenges does the chip design face? Chip design faces challenges like heat dissipation, power efficiency, and keeping up with Moore’s Law.
5. What’s the role of AI in chip design? AI plays a growing role in automating design processes, optimizing chip performance, and exploring new design possibilities.

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