Optimizing DDR Module PCB: Expert Design Tips

01

DDR Circuit Introduction

The RK3588 DDR controller interface supports the JEDEC SDRAM standard interface. The schematic circuit diagram for 16-bit data signals is shown in Figure 8-1, while the address and control signals are shown in Figure 8-2, and the power signals are shown in Figure 8-3. The circuit controller has the following features:

1. Compatible with LPDDR4/LPDDR4X/LPDDR5 standards.
2. Supports a 64-bit data bus width, consisting of 4 16-bit DDR channels. Each channel can address a maximum of 8GB, and the total capacity supported by the 4 channels can reach up to 32 GB.
3. Two 16-bit channels form a 32-bit channel. The two 32-bit channels (CH0 and CH1 in the diagram) cannot have different capacity configurations, such as 4GB+2GB.
4. Supports Power Down, Self Refresh, and other modes.
5. Features programmable outputs with dynamic PVT compensation and ODT impedance adjustment.

02

DDR Circuit Design Recommendations

Here are the DDR Circuit Design Recommendations:

1. Keep the RK3588 DDR PHY and DRAM chip schematic consistent with the original design from Rockchip, including the decoupling capacitors for the DDR power section.
2. RK3588 supports LPDDR4/LPDDR4X and LPDDR5, which have different I/O signals. Select the appropriate signals based on the type of DRAM being used.
3. Do not support swapping the DQ and CA sequences. If PCB routing requires pin adjustments, coordinate with Rockchip’s FAE (Field Application Engineer).
4. For LPDDR4/4X/LPDDR5 chips, the ZQ pins must be connected to 240 ohms ±1% and tied to the VDDQ_DDR_S0 power supply.
5. For LPDDR4/4X chips, the ODT_CA pins must be connected to 10K ohms ±5% and tied to the VDD2_DDR_S3 power supply.
6. During the built-in Retention function, the DDR controller’s DDR_CH_VDDQ_CKE power pin should remain powered when DDR enters the self-refresh period. Other power supplies can be turned off. The VDDQ power supply for DDR chips can also be turned off after 5ns of CKELCK is disabled, while other power supplies should remain on.
7. LPDDR5 introduces the WCK clock. LPDDR5 has two working clocks: CK_t and CK_c for controlling command and address operations, and WCK_t and WCK_c. WCK can run at 2x or 4x the CK frequency. During Write operations, WCK serves as the clock and Write data strobe. During Read operations, WCK is the clock for DQ and RDQS, where RDQS is the Read data strobe signal.
8. RK3588 supports DVFSC Mode when operating with LPDDR5. DVFSC Mode allows switching between VDD2L (0.9V) and VDD2H (1.05V) voltage levels. High-frequency operation uses VDD2H voltage, while low-frequency operation uses VDD2L voltage.

03

DDR Topology Structure and Matching Design

1. For LPDDR4/4x with 2 chips of 32-bit, DQ and CA should use a point-to-point topology structure, as shown in Figure 8-4. The matching method involves LPDDR4 chips, where DQ, CLK, CMD, and CA all support ODT. All of them should be connected in a point-to-point manner.
2. For LPDDR5 with 2 chips of 32-bit, DQ and CA should also use a point-to-point topology structure, as shown in Figure 8-5. The matching method here is for LPDDR5 chips, where DQ, CLK, CMD, and CA all support ODT. Connect all of them in a point-to-point manner.

04

DDR Power Design and Power-Up Timing Requirements

The power supply summary for the RK3588 DDR PHY is shown in Table 8-1:

The power supply summary for LPDDR4/4X/LPDDR5 chips is as shown in Table 8-2:

05

DDR Power Supply Design Circuit Recommendations

Power Supply Circuit for Dual PMIC Configuration

When using the Rockchip RK806-2 PMIC, it is important to note that, depending on the actual DRAM chips used, you should simultaneously adjust the feedback resistor (RK806-2 FB9, pin 66) to match the output voltage VDDQ_DDR_S0 with the chip, as shown in Figure 8-6.

When using the Rockchip RK806-2 PMIC, it is essential to adjust the feedback resistor value (RK806-2 FB9, pin 66) based on the actual DRAM chips in use. This adjustment is necessary to match the output voltage VDD2_DDR_S3 with the specific chips, as illustrated in Figure 8-7.

Power Supply Circuit for Single PMIC Configuration

When using the Rockchip RK806-1 PMIC, it is crucial to adjust the feedback resistor value (RK806-1 FB9, pin 66) simultaneously based on the actual DRAM chips in use. This adjustment is necessary to match the output voltage VDDQ_DDR_S0 with the specific chips, as illustrated in Figure 8-8.

When using the Rockchip RK806-1 PMIC, it is essential to adjust the feedback resistor value (RK806-1 FB6, pin 31) simultaneously based on the actual DRAM chips in use. This adjustment is necessary to match the output voltage VDD2_DDR_S3 with the specific chips, as illustrated in Figure 8-9.

In the Rockchip factory-original RK3588 circuit schematic reference template, compatibility is provided for both LPDDR4 and LPDDR4x designs. It’s crucial to choose the appropriate circuit based on the actual components. When using LPDDR4 chips, only attach resistor R3811, and do not attach R3808. When using LPDDR4x chips, only attach resistor R3808 and do not attach R3811, as illustrated in Figure 8-10.

06

DDR Circuit Layering and Impedance Design

8-Layer Through-Hole Board with 1.6mm Thickness – Layering and Impedance Design

In the 8-layer through-hole board layering design, the reference planes for the top layer signal (L1) are on L2, and the reference planes for the bottom layer signal (L8) are on L7. It is recommended to stack the layers as TOP-Gnd-Signal-Power-Gnd-Signal-Gnd-Bottom, with a recommended copper thickness of 1oz throughout and a board thickness of 1.6mm. For a detailed layering and impedance design process, please refer to Chapter 2 of the whitepaper. The recommended layer stacking is illustrated in Figure 8-11, and the impedance line width and spacing are shown in Figure 8-12.

10-Layer 1st Order HDI Board with 1.6mm Thickness – Layering and Impedance Design

In the 10-layer 1st-order board layering design, the reference planes for the top layer signal (L1) are on L2, and the reference planes for the bottom layer signal (L10) are on L9. It is recommended to stack the layers as TOP-Signal/Gnd-Gnd/Power-Signal-Gnd/Power-Gnd/Power-Gnd/Power-Signal-Gnd-Bottom. For L1, L2, L9, and L10, it is suggested to use 1oz copper, while other inner layers can use half-ounce (0.5oz) copper. For a detailed layering and impedance design process, please refer to Chapter 2 of the whitepaper. The recommended layer stacking is illustrated in Figure 8-13, and the impedance line width and spacing are shown in Figure 8-14.

10-Layer 2nd Order HDI Board with 1.6mm Thickness – Layering and Impedance Design

In the 10-layer 2nd-order board layering design, the reference planes for the top layer signal (L1) are on L2, and the reference planes for the bottom layer signal (L10) are on L9. It is recommended to stack the layers as follows: TOP-Gnd-Signal-Gnd-Power-Signal/Power-Gnd-Signal-Gnd-Bottom. For L1, L2, L3, L8, L9, and L10, it is suggested to use 1oz copper, while other inner layers can use half-ounce (0.5oz) copper. For a detailed layering and impedance design process, please refer to Chapter 2 of the whitepaper. The recommended layer stacking is illustrated in Figure 8-15, and the impedance line width and spacing are shown in Figures 8-16 and 8-17.

07

DDR Circuit Impedance Lines and Impedance Requirements

All channel data DQ and DM single-ended signal impedance should be 40 ohms. If the layering cannot meet the 40-ohm target impedance, ensure that the impedance is at least 45 ohms ±10%. This provides a larger margin for signals targeting 40 ohms and a smaller margin for signals targeting 45 ohms, as illustrated in Figure 8-18.

All channel address and control single-ended signal impedance should be 40 ohms, as shown in Figure 8-19.

The CKE single-ended signal impedance should be 50 ohms, as depicted in Figure 8-20.

All channel data strobe signals (DQS) and clock differential signals should have an impedance of 80 ohms. If the layering cannot meet the 80-ohm target impedance, ensure that the impedance is at least 90 ohms ±10%, as illustrated in Figure 8-21.

08

DDR Circuit PCB Design Timing Requirements

Due to the 8-layer board with routing on both the surface and inner layers, there are differences in signal rates between single-ended and differential signals on the surface layer. On the inner layers, the differences in single-ended and differential signals are smaller. There are also differences in the via rates and routing rates. To minimize the impact of rate differences on signal margins, design rules need to be based on equal delays.

When designing the PCB, layer parameters should be set according to the actual board manufacturing process, taking into account package delays and via delays. The specific timing requirements are shown in Table 8-3.

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