Many small whites know that everyone in the technical field hopes to understand all the relevant circuits and related timing. For most of the signal names and functions, they are not very familiar with them. Here, I list some of the main signal names for your reference. If you find it useful, I suggest you learn and specialize in chip-level computer repair. Understanding common signal functions will greatly help in your later studies. I recommend bookmarking this.
▶ Power Button #
This signal is generally familiar to everyone, whether on a motherboard or a laptop; there is a power-on signal. Manufacturers typically abbreviate it as POWER_SW#, ON/OFFBTN#, PWRBTN#, NBSWON#, KBC_PWR_BTN#. This power-on signal triggers SMI# or SCI to indicate a system request to enter sleep mode. If the system is already in sleep mode, this will result in a wake-up event signal. If the PWRBTN# key is held for more than 4 seconds, it will unconditionally transition (power button override) to the S5 state. This override can occur even if the system is in states S1-S4.
▶ SLP_S0 #
S0 – In fact, this is our usual working state, where all devices are powered on, and power consumption typically exceeds 80W.
▶ SLP_S1# #
S1 – Also known as POS (Power on Suspend), in this state, besides shutting down the CPU through the CPU clock controller, other components continue to function normally. Power consumption during this state is generally below 30W; (In fact, some CPU cooling software utilizes this operating principle).
▶ SLP_S2# #
S2 – In this state, the CPU is in a halted state, and the bus clock is also turned off, but the remaining devices continue to operate.
▶ SLP_S3# #
S3 – This is what we commonly know as STR (Suspend to RAM), and power consumption during this state does not exceed 10W. This signal is used on all platforms and is something we need to check in actual repairs. If there is an issue with this signal, it can lead to problems like no power-on or unexpected reboots.
▶ SLP_S4# #
S4 – Also known as STD (Suspend to Disk), in this state, the system’s main power is turned off, but the hard drive remains powered and can be awakened. This signal is used on all platforms and is something we need to check in actual repairs. If there is an issue with this signal, it can lead to problems like no power-on or unexpected reboots.
▶ SLP_S5# #
S5 – This state is the most straightforward, where all devices, including the power source, are completely turned off, resulting in zero power consumption. When entering the S5 state, all devices cease operation.
▶ SLP_A# #
This signal is a newly added signal that emerged after the integration of the North and South Bridge, introduced since our i-series platforms. This signal, SLP_A#, is used by the PCH to activate the Active Sleep Well (ASW) circuit within the PCH. It originates from Intel Management Engine technology and Intel Active Management Technology, abbreviated as ME technology and AMT technology. With the support of these two new technologies and dedicated software, computer management can be performed over the Internet.
SLP_A# is employed to control the power supply of the PCH’s ME module. PS: This signal may have previously been in a high-level state, meaning it can be configured differently based on design requirements. However, this signal will never be active after SLP_S3#.
▶ SLP_LAN# #
This signal is also a newly added one and exists in conjunction with the SLP_A# signal. Due to the need to support ME technology, the PCH must control the power supply to the external Ethernet module in order to enable software supported by AMT technology to start or shut down the computer through Ethernet. When the motherboard is powered correctly, both SLP_A# and SLP_LAN# must be at a high level.
PS: This signal may also have been in a high-voltage state previously (in cases where Wake-On-LAN network wake-up is supported). However, this signal will never be active after SLP_A#. When all SLP signals are at a high level, the EC (Embedded Controller) sends a voltage enable signal to activate the S0 voltage, also known as the RUN voltage.
▶ VccASW #
This voltage is also a newly introduced power supply, intended for the operation of ASW (Active Sleep Well). Its voltage level is 1.05V, and it is used to power the AMT module and the network card module.
▶ CPU_SVID #
When PROCPWRGDY becomes active, the CPU sends a set of CPU_SVID signals to the CPU VRM power chip. These signals consist of a standard serial bus composed of DATA and CLK, along with an ALERT# signal that serves as a wake-up indicator.
▶ VccCore_CPU #
It’s easy to understand. The power supply to the CPU is established by the power management IC, which combines the CPU_SVID signals and transmits the predetermined information to the CPU for its operating voltage.
▶ SYS_PWROK #
This signal is a power good indication sent from the CPU VRM chip to the PCH (Platform Controller Hub) once the CPU VCORE voltage stabilizes and becomes steady. This signal indicates that the CPU VCORE power supply is operating normally.
▶ PWROK #
When the primary voltages are all active and stable, a PWROK signal is released to the PCH (usually monitored and generated by the EC), notifying the PCH that all RUN voltages are ready.
▶ APWROK #
This signal is also a newly introduced one and is typically sent from the EC (Embedded Controller) to the PCH after monitoring that the ASW power supply is active and stable, indicating the stability of the ASW module power supply.
▶ DRAMPWROK #
This signal is connected to the CPU’s SM_DRAMPWROK pin. PCH emits this signal to indicate that the DRAM (memory) voltage is stable.
▶ PROCPWRGD #
This signal is emitted by the PCH and sent to the CPU’s UNCOREPWRGOOD pin, indicating that the CPU’s power supply is stable.
▶ SUS_STAT# #
This signal indicates that the system has entered a suspended state. It is asserted by the PCH to declare that the system has entered a low-power state, and it can also be used for other peripheral devices to trigger their output shutdown. This signal should be driven to a high level during normal startup processes.
▶ THRMTRIP# #
This signal is used to monitor the core temperature of the CPU. When the detected temperature rises to its limit, the THRMTRIP# signal is driven low. Upon receiving a low-level THRMTRIP# signal, the PCH immediately drives the SLP_S5# signal low, causing the entire system to enter the S5 state and cut off power. This is what is commonly referred to as a power-off due to temperature issues.
PS: Before PROCPWRGD becomes active, the THRMTRIP# signal can be ignored. It only functions after PROCPWRGD becomes active. This signal is typically in a high-level state under normal conditions and is only driven low in the event of a circuit malfunction or excessively high CPU temperature.
▶ PLTRST# #
This signal is the overall platform’s general reset signal. When SUS_STAT# is driven high for 60 microseconds, PLTRST# is also driven high, completing the reset for other devices and the CPU.
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