SRAM is frequently used for data storage in chip design, such as in FIFO, Queue, and cache structures. However, due to the variety of SRAM types and parameters, selecting the appropriate SRAM is crucial. This article mainly introduces the principles of SRAM and common usage guidelines.
01
Basic Principle of SRAM
SRAM stands for Static Random Access Memory. It is a type of memory that stores data using flip-flops, with each memory cell typically composed of six transistors forming a bistable circuit.
This type of circuit has two stable states representing data values of 0 and 1. As long as power is supplied, the data remains stable without requiring periodic refreshing like DRAM. Hence, “static” refers to the data being stably retained while powered, although it will be lost once power is removed.
02
Common Classifications of SRAM
By Port Type: SRAM can be classified as Single-Port (SP), Pseudo Dual-Port (Two-Port, TP), and True Dual-Port (DP).
- Single-Port SRAM: Has only one port, i.e., one set of data and address lines, allowing only one read or write operation at a time, not both simultaneously.
- Pseudo Dual-Port SRAM: Has two ports, but one is read-only and the other write-only. It has separate write address and data lines, as well as read address and data lines, enabling simultaneous read and write operations.
- Dual-Port SRAM: Has two ports with two sets of address and data lines. Each port supports both read and write operations, allowing true simultaneous read and write access.
By Voltage Threshold (VT): SRAM can be categorized as HVT (High VT), SVT (Standard VT), LVT (Low VT), and ULVT (Ultra Low VT). Lower threshold voltages offer higher speeds but consume more power, requiring a balance between timing and power consumption.
By Error Checking Method: It can be classified into parity check, ECC check, etc.
- Parity Check: Simple to implement and low-cost. A parity bit is added to the data. For odd parity, the total number of 1s including the parity bit is odd; for even parity, it is even. Parity check can only detect odd-numbered bit errors and has no error correction capability.
- ECC Check: Commonly uses Single Error Correction and Double Error Detection (SEC-DED), which introduces minimal delay during encoding and decoding, making it suitable for high-speed paths.
By Manufacturer: Common SRAM vendors include TSMC, Synopsys, Samsung, etc.
03
General Guidelines for Using SRAM
In chip design, factors such as timing, area, and power consumption must be considered to select suitable SRAM.
- Port Type Selection: Generally, single-port SRAM is preferred, followed by pseudo dual-port SRAM. True dual-port SRAM is not recommended due to its larger area and power consumption.
- VT Type Selection: SVT or LVT are generally preferred to reduce power consumption while meeting timing requirements.
- Error Checking Selection: Parity check is low-cost and simple, suitable for cost-sensitive scenarios where error detection is not critical, such as FIFO checking. On-chip SRAM typically uses SEC-DED ECC, which can effectively correct single-bit errors and detect double-bit errors.
SRAM supply can be either dual-rail or single-rail. Dual-rail has two power lines: VDDCORE and VDDM, with a required voltage drop of less than 0.5mV. Replacing dual-rail with single-rail may yield about 3% area savings and 10% static power savings. However, this is rarely done because a single VDD makes it more susceptible to voltage drops from external digital logic loads, which may cause errors in adjacent bits.
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