01
The Development of Optical Communication Technology
The development of information technology has driven the progress of human information society. From signal fires to relay stations, from wireless telegraphy to wired telephones, people have been moving toward faster, more convenient, and larger-capacity communication methods.
In 1966, Dr. Charles K Kao proposed the theory of low-loss optical fibers, which made fiber-optic communication (transmitting information through light) possible.
Optical fiber communication has numerous advantages, such as large bandwidth, low loss, long distance, large capacity, and resistance to electromagnetic interference. With the rapid development of low-loss optical fibers and semiconductor lasers, optical fibers have gradually replaced copper wires, wireless, and many other traditional transmission methods, becoming the primary technology for digital communication.
In the early 1990s, the invention of Erbium-Doped Fiber Amplifiers (EDFA) and Wavelength Division Multiplexing (WDM) technologies made long-distance, high-speed optical relay transmission possible. By increasing the number of transmission channels, transmission capacity has experienced explosive growth.
In Wide Area Networks (WANs) and Metro Area Networks (MANs), optical fiber communication has been rapidly adopted and has become dominant. As optical communication technology continues to develop and the demand for higher communication speeds grows, optical fiber communication has gradually been applied in shorter-distance communication networks, such as Local Area Networks (LANs) and Access Networks (ANs). The Fiber-to-the-Home (FTTH) technology has also been widely adopted worldwide.
Driven by emerging applications such as ChatGPT, big data, artificial intelligence, and industrial internet, high-speed optical transmitter chips for data center applications will handle a global data traffic of 175 Zettabytes by 2025.
On one hand, short-distance communication requires further capacity enhancement, while the power consumption needs to be reduced. On the other hand, with the continuous improvement in the processing accuracy of microelectronic devices, the feature size of Complementary Metal Oxide Semiconductor (CMOS) processes has been reduced, reaching the physical limit for electronic transmission, which hinders further increases in communication speed (single-channel electrical interconnect speed < 25 Gb/s). Therefore, optical interconnects replacing electrical interconnects and further improving communication bandwidth has become an inevitable trend.
To meet the growing traffic demands, optical transceiver modules for data centers are expected to provide transmission capacities of 800 Gbit/s or higher.
The transmission distance and speed requirements vary depending on the architecture of the data center.
02
Overview of Data Center Architecture
The Spline-leaf architecture adapts to the development trend of data centers. It is divided into the cabinet layer, Leaf layer, and Spline layer.
The cabinet layer is responsible for placing servers, which are interconnected through Top-of-Rack (ToR) switches. The cabinet layer is the lowest layer of the network architecture, requiring a transmission bandwidth of 200G and a transmission distance of 4–20 m.
The Leaf layer consists of leaf switches and connects to both ToR switches and Spline switches.
The Leaf layer acts as an intermediary, and the transmission rate requirement between the Leaf layer and ToR is 800G, with a transmission distance of approximately 100 m (SR).
The Spline layer is the top layer of the data center structure. Its role is twofold: first, it interconnects the internal Spline-Leaf layers, with a transmission bandwidth of 800G and a transmission distance of 2 km (FR); second, it realizes inter-data center (Inter-Data Center, DCI) interconnections, with transmission distances of 80–120 km (ZR), typically using dense wavelength division multiplexing (DWDM) technology or coherent optical modules.
Over the past few decades, silicon photonics has become a disruptive optoelectronic technology capable of meeting the growing bandwidth density, integration, and energy efficiency demands of data centers.
03
Classification of Photonic Integrated Chip Materials
Similar to electronic integrated chips, Photonic Integrated Circuits (PICs) can fabricate complex optical network systems on a single chip. These chips can be highly integrated, and CMOS-compatible processes ensure large-volume production, lowering chip manufacturing costs.
Photonic integrated chips avoid the alignment and packaging issues associated with free-space optical components, greatly improving system stability and benefiting large-scale production. However, to this day, photonic integrated chips have not developed as rapidly as microelectronics. The reason is that the materials used for fabricating photonic integrated chips are numerous, and no unified standard for defining photonic integrated chips has been established. Some mainstream material platforms include Silicon Photonics (SiPh), Indium Phosphide (InP), Lithium Niobate (LiNiO3), Planar Lightwave Circuits (PLC), and polymer planar lightwave guide platforms.
The Silicon Photonics platform uses silicon as the core waveguide material, with a refractive index of about 3.48 (at 1.55 µm). Because of the large refractive index contrast between the core and cladding, silicon waveguides are very compact, and their bending radius can reach several micrometers or even a few microns. The process is fully compatible with microelectronic CMOS technology, making it advantageous for large-scale integration and high-volume production. However, silicon is an indirect bandgap semiconductor and cannot emit light, so it cannot be used for light sources or optical amplifiers. Additionally, silicon has a centrosymmetric crystal structure, which lacks the linear electro-optic effect (Pockels effect), preventing the realization of high-speed electro-optic modulators. Finally, silicon has a low optical absorption rate in the communication band, so it cannot be used to fabricate efficient photodetectors.
Indium Phosphide (InP) is a representative III-V material, a direct bandgap semiconductor capable of fabricating lasers, high-speed modulators, detectors, and optical amplifiers.
However, the refractive index difference between the core and cladding of the InP platform is small, resulting in larger device sizes and bending radii, and it is incompatible with CMOS processes, making manufacturing costly and unfavorable for large-scale integration.
Lithium Niobate (LiNbO3) is often used in modulator fabrication. The commonly used lithium niobate crystal utilizes its inherent linear electro-optic effect for electro-optic modulation. These modulators require long modulation arms to achieve a low half-wave voltage, resulting in large structures typically on the order of 10 cm, which is not suitable for integration. In recent years, the development of Lithium Niobate on Insulator (LNOI) has solved the integration problem, but current processing technologies are still quite complex, and costs are high.
Silicon dioxide (SiO2) planar lightwave circuit devices are the only material platform currently achieving commercial success. Silicon dioxide optical waveguides have a small refractive index difference between the core and cladding, large waveguide sizes, and very low transmission loss. They can efficiently couple with single-mode fibers. However, silicon dioxide has a very low thermo-optic coefficient (1.19×10-5/K) and does not have electro-optic effects, so it cannot achieve efficient tuning.
Polymer planar lightwave guides, using polymer materials like SU8 as the waveguide core and cladding, have a thermo-optic coefficient of -1.86×10-4/K, making them suitable for low-power thermal-optical devices. Additionally, polymers have the characteristic of being synthesizable, enabling the integration of various functions such as electro-optical properties, amplification, and biosensing, making it a highly promising photonic chip platform.
In summary, each material platform has its advantages and disadvantages, and no single material can meet all the needs of photonic integrated chips for light sources, passive components, modulators, and detectors. To integrate all functions, hybrid integration will be a solution.
04
Overview of the Silicon Photonic Modulator Fabrication Process
Most foundries offer three types of chip manufacturing services: multi-project wafer (MPW), custom services, and mass production.
MPW allows multiple designers to share the same mask and manufacturing process, with manufacturing costs shared among the designers.
Using a 200 mm CMOS standard process, the silicon substrate thickness is about 750 µm, with a resistivity greater than 750 Ω-cm. The thickness of the buried oxide (BOX) layer is 3 µm, and the top silicon layer thickness is 220 nm.
The first etching depth is 70 nm for fabricating the grating coupler; the second etching continues to 60 nm, leaving a remaining thickness of 90 nm for fabricating the ridge waveguide.
After defining the grating coupler and waveguide and completing the etching, ion implantation is performed in P++, N++, P+, N+, P, and N regions, with boron (B) and phosphorus (P) used as dopants for P-type and N-type, respectively.
Next, metal deposition is performed to form the ohmic contacts for the flat N++ and P++ regions. The first via (Via 1) and the first metal layer (Metal 1) are connected, with Via 1’s height about 600 nm and Metal 1’s thickness about 750 nm.
Metal 1 and the second metal layer (Metal 2) are connected via the second via (Via 2), with Via 1’s height about 1310 nm and Metal 1’s thickness about 2000 nm. Both Metal 1 and Metal 2 are made of aluminum.
According to the AMF design manual, the design and fabrication of the silicon electro-optic modulator have been completed. The microscope images (a)-(b) show the fabricated DD-MZM and SPP-MZM.
The modulator’s traveling-wave electrode integrates a matching resistor made of TiN, with a design resistance of about 35 Ω. The modulation arm length is 2 mm, using an asymmetric MZM structure, and the modulator’s bias point can be controlled by tuning the wavelength. Later, a symmetric MZM can be used to overcome the wavelength sensitivity of the asymmetric MZM.
05
Packaging Technology for Silicon Photonics
In recent years, photonic integrated chips have rapidly developed in both function and scale. However, limited by the types of materials and photolithography sizes, two-dimensional integrated photonic chips can no longer meet the demands for chip integration and the number of optical I/Os.
To achieve larger-scale, multi-port photonic integrated chips with more complex functions, researchers have conducted extensive studies on three-dimensional photonic integrated chips.
Initially, three-dimensional integration was realized in integrated circuits, where each layer of multi-layer circuits is interconnected using through-silicon vias (TSVs), improving routing flexibility and reducing power consumption, delay, and noise caused by long wiring. This increased the communication capacity and bandwidth.
Similarly, in the photonic integrated chip field, optical vias (TSOVs), or through-silicon optical vias, can be introduced. These vias function similarly to TSVs, enabling the connection of multi-layer photonic chips, increasing the number of photonic devices per unit area, i.e., the integration level.
An additional benefit is that, compared to in-layer waveguide crossings, waveguide crossings between layers exhibit very low loss and minimal crosstalk due to optical physical isolation.
Wafer bonding also enables heterogeneous integration between different materials, commonly used for bonding III-V optical chips with SOI/SiN wafers to achieve high-quality light source fabrication on the chip.
Due to the limitations of modulators, signal integrity, and integration level, board-level optical (OBO) pluggable optical modules will reach a technical bottleneck after 1.6T.
Beyond 1.6T, the most promising solution in the industry is co-packaged optics (CPO) technology.
CPO technology involves packaging the core switching chip (ASIC) and the photonic engine onto the same carrier, using an interposer for high-speed collaborative packaging.
CPO significantly shortens the distance between the photonic engine and the ASIC chip, reducing link losses.
That concludes the introduction to optical communication chip technology. Stay tuned to our website to learn more about semiconductor technology!
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