01
What is CoWoS
CoWoS is strictly considered a 2.5D advanced packaging technology, derived from the combination of CoW and oS: first, the chip is connected to the silicon wafer via Chip on Wafer (CoW) packaging process, and then the CoW chip is connected to the substrate, integrating into CoWoS. The core idea is to stack different chips in the same silicon interposer to achieve interconnection between multiple chips.
Since its development by TSMC in 2011, CoWoS has undergone five iterations of technology; TSMC divides CoWoS packaging technology into three types—CoWoS-S, CoWoS-R, and CoWoS-L, with differences in technical characteristics and applications.
TSMC divides CoWoS packaging technology into three types—CoWoS-S, CoWoS-R, and CoWoS-L. The main difference lies in the different interposer layers:
02
Advantages of CoWoS
High integration: A significant feature of CoWoS packaging technology is its ability to achieve high integration, meaning multiple chips in one package can be highly integrated, thus providing more powerful functionality in a smaller space. This technology is particularly suitable for industries with high space efficiency demands, such as the internet, 5G, and artificial intelligence.
High speed and high reliability: Since the chip is directly connected to the wafer, CoWoS packaging technology can improve signal transmission speed and reliability. Additionally, it effectively shortens the signal transmission distance, reducing transmission latency and energy loss.
Cost-effectiveness: Compared to traditional packaging technologies, CoWoS technology can reduce chip manufacturing and packaging costs. This is because it avoids cumbersome steps in traditional packaging, such as copper wire winding and high material costs, thereby improving production efficiency and reducing costs.
03
Challenges of CoWoS
Manufacturing complexity: CoWoS is a 2.5D/3D integration technology, and compared to previous technologies, its manufacturing complexity has significantly increased. The increased manufacturing complexity directly results in higher costs for chips using this packaging technology.
Integration and yield challenges: 2.5D and 3D integrated circuits need to be tested, just like any other integrated circuit, to ensure there are no manufacturing defects. However, testing 2.5D or 3D integrated circuits is much more difficult because each wafer chip needs to be tested individually before being installed onto the interposer, and it needs to be tested again after installation. Additionally, through-silicon vias (TSV) need to be tested. Finally, large silicon interposers are particularly susceptible to manufacturing defects, which could lead to yield loss.
Electrical challenges: Signal integrity: Interconnection from the logic wafer to the substrate: As data rates increase, signal transmission degrades due to parasitic capacitance and inductance from the TSVs. To solve this, efforts are being made to optimize TSVs to minimize capacitance and inductance. Logic wafer chip to HBM: The eye diagram performance bottleneck of the interconnection between SoC and HBM is due to parasitic resistance and capacitance. Power integrity: CoWoS packaging is often used for high-performance applications with high data switching rates and low operating voltages, making these packages susceptible to power integrity challenges.
Thermal challenges: Due to the differing coefficients of thermal expansion (CTE) between the interposer and the substrate, CoWoS packaging faces thermal management issues. Using organic interposers can somewhat mitigate thermal issues. Bottom-up filling materials can buffer the thermal mismatch between the silicon wafer and substrate, significantly improving the lifespan of solder joints.
04
CoWoS Development in China
Although TSMC dominates the global CoWoS packaging technology market, China’s semiconductor industry has also made some progress in CoWoS packaging technology. Some domestic companies have begun to enter the CoWoS packaging field and are working hard to narrow the gap with international advanced levels.
Research and development of CoWoS packaging technology in China’s semiconductor industry has been relatively lagging, mainly due to limited domestic accumulation in packaging technology and a lack of collaboration and exchange with leading global companies. However, in recent years, some domestic companies have started to increase their investment in CoWoS packaging R&D and have achieved some initial results.
For example, companies like JCET and Tongfu Microelectronics have strong capabilities in traditional packaging, but they are also working hard to catch up in high-end packaging technologies like CoWoS. JCET has focused on high-performance advanced packaging technology in recent years, achieving innovative breakthroughs in automotive electronics, 5G communication, and high-performance computing. Tongfu Microelectronics has facilities in both China and overseas and engages in Chiplet packaging, along with production of the front-end interposer.
In addition, some emerging companies in China are starting to engage in CoWoS packaging, such as Shenghe Jingwei. Shenghe Jingwei is a partner in Huawei’s ecosystem, completing advanced packaging for Huawei’s Ascend and Kunpeng chips while also engaging in Chiplet packaging and production of front-end interposers.
In the development of CoWoS packaging technology, collaboration and synergy among upstream and downstream companies in the industry chain are crucial. China’s semiconductor industry is strengthening cooperation among upstream and downstream enterprises to jointly promote the development of CoWoS packaging technology.
For instance, in packaging equipment, some domestic companies have started R&D and production of CoWoS packaging equipment. Leading domestic companies in the packaging equipment sector, such as Xinqi Microelectronics’ LDI laser direct write lithography technology, Xinyi Chang’s die bonding technology, Guangli Technology’s dicing technology, and Jintuo’s pick-and-place technology, are all top players. These companies have provided strong support for the development of domestic CoWoS packaging technology.
In packaging materials, some domestic companies have begun R&D and production of CoWoS packaging materials. Materials such as Jiangfeng Electronics’ target materials, Yuheng New Materials’ electroplated nickel, Feike Materials’ photoresist and temporary bonding technology, and Qiangli New Materials’ electroplating liquids and PSPI are important components of the domestic packaging materials industry. These materials provide solid support for the development of domestic CoWoS packaging technology.
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