The global terminal market has yet to fully recover, and competition in the semiconductor industry is becoming increasingly fierce. At the same time, AI is driving demand and technological upgrades in semiconductors. Against this backdrop, companies are accelerating breakthroughs in advanced semiconductor processes and packaging technologies. Recently, several developments have emerged in the market: Intel’s 18A process has entered the risk production phase; Rapidus plans to launch 2nm chip samples; Samsung is accelerating 2nm process development; and TSMC is pushing forward in both advanced processes and packaging.
01
Intel 18A Process Enters Risk Production Phase
At the recent Intel Vision 2025 conference, Intel officially announced that its 18A process technology has entered the risk production phase. With the progress of the 18A process, Intel’s next-generation processor “Panther Lake” is expected to begin mass production this year.
Industry sources revealed that “risk production” is a critical stage before full-scale mass production, where foundries begin small-batch pilot production using new process technologies to verify process stability, yield, and design rule correctness. Though there is still a long way to go before mature mass production, reaching this stage already demonstrates Intel’s strength and determination in advanced process technology.
According to available information, the biggest highlights of Intel’s 18A process are two breakthrough technologies: RibbonFET and PowerVia.
RibbonFET is a new transistor structure, also known as Gate-All-Around (GAA) technology. Compared to traditional FinFETs, RibbonFET wraps the channel material around all four sides of the gate like nano-scale “ribbons.” This design enables better control of current switching, reduces leakage, and delivers higher performance and energy efficiency in smaller spaces—a major innovation that paves the way for future smaller process nodes.
PowerVia focuses on the chip’s power delivery method. Traditionally, power and signal interconnections are made on the same side of the chip, which can lead to signal congestion and voltage drop. PowerVia shifts power interconnections to the back of the chip, delivering power directly to transistors. This frees up the front side for signal routing, improving signal transmission efficiency, reducing power consumption, and enhancing overall performance.
Intel disclosed that compared to the Intel 3 process, 18A offers up to 15% better performance per watt and 30% higher chip density. These improvements will translate directly into competitive advantages across Intel’s product lines.
The industry points out that Intel’s 18A process is technologically comparable to TSMC’s N2 (2nm-class) process. Intel may hold a performance edge, while TSMC may achieve higher transistor density. Intel’s PowerVia backside power delivery is a unique advantage, and TSMC is not expected to adopt similar technology until its A16 process (2026–2027).
02
Rapidus Plans to Launch 2nm Chip Samples
On April 1, Japanese semiconductor company Rapidus announced that its 2025 fiscal plan and budget had been approved by Japan’s New Energy and Industrial Technology Development Organization (NEDO), and it will start its 2nm chip pilot production line in April, aiming for mass production in 2027.
Industry experts note that 2nm is one of the most advanced semiconductor manufacturing processes. If Rapidus can successfully launch and mass-produce 2nm chips, it would mark a major breakthrough for Japan in semiconductor manufacturing, narrowing the gap with leaders such as TSMC and Samsung.
The launch of 2nm chip samples by Rapidus is undoubtedly a significant milestone in Japan’s semiconductor revival, showcasing the country’s determination and potential to reclaim its place in the industry.
However, it’s important to note that producing samples and achieving mass production are vastly different, and Rapidus as well as Japan’s semiconductor sector still face challenges in technology, funding, and supply chain.
03
Samsung Accelerates 2nm Process Development
Although Samsung has faced setbacks at the 3nm node, it remains committed to advancing its cutting-edge process technology.
The latest news indicates Samsung is about to begin prototype mass production of the world’s first 2nm chip, the Exynos 2600, in May 2025. The Galaxy S26 series, set to launch early next year, will be the first to feature this chip.
The Exynos 2600 is based on Samsung’s SF2 process, its first-generation 2nm node. Compared to its 3nm process, SF2 reduces power consumption by 25%, increases performance by 12%, and reduces chip area by 5%, under the same clock speed and complexity.
Currently, the Exynos 2600 yield rate is around 30%, but as mass production advances, yields are expected to improve. At the same time, Samsung is working to maintain high performance while tightly controlling power consumption.
Beyond this product, Samsung has planned multiple process nodes including SF2P, SF2X, SF2Z, and SF2A, targeting high-performance computing, AI, and automotive applications.
04
TSMC Advances in Both Advanced Process and Packaging
On March 31, TSMC held a “2nm expansion ceremony” at its Kaohsiung plant (Fab 22), marking the structural completion of Phase 2 (P2) with a topping-off ceremony.
TSMC Executive VP and Co-COO Y.P. Chin stated that Kaohsiung and Tainan sites will form the “world’s largest semiconductor manufacturing cluster,” and that the 2nm process is progressing as scheduled, with mass production expected in the second half of 2025. Compared to 3nm, the 2nm process offers a 10%–15% speed boost at the same power or 25%–30% power savings at the same speed.
The Kaohsiung site is planned to have five phases. Progress is on schedule: Phase 1 (P1) is already installing equipment; Phase 2 completed its structure; Phase 3 (P3) has begun structural construction; Phases 4 (P4) and 5 (P5) have passed environmental reviews this month.
To meet demand for high-performance chips, TSMC is aggressively investing in both advanced process and advanced packaging capacity. Recently, TSMC held an expansion ceremony at its advanced packaging AP8 plant in Taiwan’s Southern Science Park. The goal is to boost capacity for advanced packaging, especially CoWoS technology.
AP8 is TSMC’s largest advanced packaging facility, with cleanroom space nearing 100,000 square meters. To meet surging AI demand for CoWoS, TSMC is upgrading the plant and mobilizing supply chain partners to install equipment, expected to begin as early as April 2025, with mass production potentially starting in the second half of the year.
According to TrendForce, combining AP8, a facility acquired from Innolux, and the Taichung plant, TSMC’s monthly CoWoS capacity could reach a record 75,000 wafers in 2025—almost double that of 2024.
Alongside TSMC, other major players including Intel and Samsung are also heavily investing in advanced packaging technologies to offer integrated solutions. Intel’s EMIB and Foveros, and Samsung’s I-Cube and X-Cube, are all positioned to compete with TSMC’s CoWoS. This signals that in the AI era, competition in semiconductors extends beyond advanced process nodes—advanced packaging has also become a key battleground.
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