It was previously reported that Samsung has chosen to build a 1cnm DRAM production line at its Pyeongtaek P4 factory and has ordered equipment from partners, with installation expected to begin in the first quarter of 2025, paving the way for HBM4 production. The 1cnm process belongs to the sixth generation of 10nm-class technology, with a line width of approximately 11-12nm, ahead of the existing fifth-generation 10nm-class 1bnm (with a line width of approximately 12-13nm). Samsung aims to start mass production in June 2025.
According to TrendForce, since the second half of 2024, Samsung has been adjusting the design of the 1cnm DRAM due to the familiar issue of yield rates. Samsung’s 1cnm DRAM has faced yield rate issues since its development, and the trial production at the end of 2024 did not meet expectations. The yield rate during the mass production preparation phase typically ranges from 60% to 70%.
Samsung’s new approach focuses on maintaining compact core line widths while relaxing the line widths of peripheral circuits, thereby improving yield rates to ensure stable mass production of high-value memories such as HBM. A significant improvement is expected to be seen between May and June of this year. Samsung hopes to complete the adjustment as soon as possible, as its competitor SK Hynix is expected to start mass production of 1cnm DRAM chips as early as February 2025, becoming the world’s first memory supplier to produce DRAM chips using the 1cnm process.
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