Increasing the stacked junction interface from 1024 bits to 2048 bits will be the biggest change in HBM memory technology ever. Because since 2015, all HBM stacked junction interfaces have been using the 1024-bit standard. However, currently, this information comes from unofficial announcements, so some reservations may still be needed for its authenticity.
According to Tom’s Hardware
At present, it is unclear whether storage manufacturers will be able to maintain a data transfer rate of approximately 9GT/s, as supported by HBM3E stacked junction interfaces, for HBM4 stacked junction interfaces with 2048-bit interfaces. However, if possible, the increase in the number of interface bits will raise the maximum bandwidth from 1.15TB/s to 2.30TB/s. Nevertheless, it is currently unclear how the increase in the number of bits per stacked memory interface will affect processor and intermediary layer usage.
Reports indicate that modern large processors, such as NVIDIA’s H100, already use large 6144-bit junction interfaces to support 6 1024-bit HBM3/HBM3E stacked memory chips (KGSD). However, whether individual memory chip interfaces will increase to 2048 bits remains to be seen, and it will depend on processor developers continuing to use the same number of HBM4 memory chip stacks.
There are also concerns that the production yield of KGSD with 2048-bit interfaces will decrease because manufacturing memory stacks with thousands of Through-Silicon Vias (TSVs) has become more challenging. However, related reports indicate that both Samsung and SK Hynix are confident in achieving a 100% yield for the new memory chips.
Recommended Reading:
Disclaimer: This article is created by the original author. The content of the article represents their personal opinions. Our reposting is for sharing and discussion purposes only and does not imply our endorsement or agreement. If you have any objections, please contact us through the provided channels.