2024: A Breakthrough Year for Advanced Packaging Tech?

IC packaging capabilities in the 2.5D and 3D era will have significant potential.

After becoming a major highlight in 2023, advanced packaging technologies continue to cause a stir this year and are closely tied to the fate of chiplets, the rising stars of the semiconductor industry. IDTechEx’s new report, “Advanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications,” explores the current landscape of advanced packaging and provides a detailed overview of emerging technologies such as 2.5D and 3D packaging.

After fabricating chips on silicon wafers using various advanced processes, foundries deliver finished wafers to packaging houses, which then cut them into individual chips, assemble or “package” them into final products, and test their performance and quality. These packaged chips are then shipped to original equipment manufacturers (OEMs).

This is part of the traditional semiconductor manufacturing value chain, where engineers build system-on-chip (SoC) on silicon wafers and then transfer them to conventional packaging processes. Moving into chiplets involves manufacturing individual system modules as separate chips or on a wafer, which are then integrated into a system through advanced packaging.

This premise has pushed advanced packaging to the forefront of innovation in semiconductor manufacturing. In fact, the future of chiplets is closely linked to advancements in advanced packaging, with 2.5D and 3D technologies rapidly taking shape to facilitate the commercialization of chiplets.

1. 2.5D and 3D Packaging

While 1D and 2D semiconductor packaging technologies still dominate many applications, future developments will involve 2.5D and 3D packaging to achieve advancements in the semiconductor field beyond Moore’s Law. These technologies utilize wafer-level integration to achieve component miniaturization, thereby increasing interconnect density.

2.5D technology facilitates a larger packaging area, requiring a shift from silicon interposers to silicon bridges or other alternatives such as high-density fan-out. However, packaging components of different materials together also presents many challenges. According to the IDTechEx report, finding suitable materials and manufacturing technologies is crucial for adopting 2.5D packaging.

Next, 3D packaging introduces new architectures, including stacking one active chip on top of another and reducing bump pitch. This 3D technology, known as hybrid bonding, is used in applications such as CMOS image sensors, 3D NAND flash, HBM memory, and chiplets. However, like 2.5D packaging, 3D packaging also faces manufacturing and cost challenges, as technologies such as hybrid bonding require new high-quality tools and materials.

2. Attraction of OSAT and EDA

The development of the ecosystem often provides important clues to the future of emerging technologies such as advanced packaging. Despite challenges, recent announcements in the semiconductor industry suggest that IC packaging capabilities in the 2.5D and 3D era hold great potential.

Amkor, a major outsourced semiconductor assembly and test (OSAT) service provider, is investing approximately $2 billion to build an advanced packaging and testing plant in Peoria, Arizona. This 55-acre facility is expected to be operational within a few years.

Additionally, Silicon Box, an advanced panel-level packaging foundry specializing in chip integration, packaging, and testing, is building a new factory in northern Italy following the establishment of its advanced packaging plant in Singapore to better serve European foundries.

EDA tool manufacturers are also eyeing this promising new field. For instance, Siemens EDA is working closely with Korean OSAT nepes to expand its IC packaging capabilities in the 3D-IC era. Siemens EDA is providing nepes with tools to tackle various complex thermal, mechanical, and other challenges associated with developing advanced 3D-IC packaging.

Siemens EDA’s Innovator3D IC toolkit (as shown above) uses a layered device planning approach to handle the massive complexity of advanced 2.5D/3D integrated designs with millions of pins. Here, the design is represented as geometric partition areas, whose attributes control refinement and implementation methods. This, in turn, allows for the rapid implementation of critical updates while matching analysis techniques to specific regions, thereby avoiding excessive execution time.

With the rapid emergence of application scenarios such as 5G communication technology, IoT, big data, AI, visual recognition, and autonomous driving, the market’s demand for diverse chip functionalities is growing. As chip process technology enters the “post-Moore era,” advanced packaging technologies can enhance product integration and functional diversity through wafer-level and system-level packaging without solely relying on chip process breakthroughs, meeting the terminal application needs for lightweight, low-power, and high-performance chips while significantly reducing chip costs.

Therefore, advanced packaging has been widely used in fields such as high-end logic chips, memory, RF chips, image processing chips, and touch chips. In the future, as the advantages of advanced packaging technologies continue to emerge, the market share of advanced packaging in the IC packaging and testing market will continue to increase, and the industry scale will continue to grow, becoming the main growth point in the packaging and testing market.

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